In general, there would be a current source control device between the current source and an output load device. The current source control device, such as a MOS transistor, always needs a gate driving circuit for providing driving voltages to control the ON/OFF state of the current source control device. The current source control device provides a driving current for the output load device when it is in the ON state.
Referring to FIG. 1, there is shown a circuit diagram of a conventional gate driving circuit of the prior art. As shown in the figure, the gate driving circuit 10 comprises a driver control circuit 11, a pull up circuit 13, a pull down circuit 15 and a PMOS transistor 17.
When the driver control circuit 11 receives an active signal, it generates a pull up signal or a pull down sign in response to the active signal. If the driver control circuit 11 generates a pull up signal according to the active signal, the pull up circuit 13 will be enabled and output a pull up voltage to the gate of the PMOS transistor 17. If the driver control circuit 11 generates a pull down signal according to the active signal, the pull down circuit 15 will be enabled and output a pull down voltage to the gate of the PMOS transistor 17.
When the pull up circuit 13 is enabled, the gate voltage VG of the PMOS transistor 17 will be pulled up to the external supply voltage VDD. In this case, the voltage difference between the source and the gate (VSG) is smaller than the threshold voltage (VT) of the PMOS transistor 17, and the PMOS transistor 17 will be turned to the OFF state. There would be no current for the output load device 19.
If the pull down circuit 15 is enabled, the gate voltage VG of the PMOS transistor 17 will be pulled down to the ground voltage. The voltage difference between the source and the gate (VSG) is larger than the threshold voltage (VT) of the PMOS transistor 17, and the PMOS transistor 17 is turned to the ON state. Then it provides a driving current for the output load device 19.
The conventional gate driving circuit 10 of the prior art has a drawback of causing an unstable driving current if the external supply voltage VDD varies or has a voltage drift. While the PMOS transistor 17 is in the ON state, the gate voltage VG is equal to the ground voltage and the source voltage is equal to the external supply voltage VDD. In this case, if the external supply voltage VDD varies, the voltage source-to-gate (VSG) varies too, thus the current that passes through the PMOS transistor 17 also varies.
The current instability caused by the conventional gate driving circuit 10 is usually harmful for the output load device 19 and other load devices. It may drive the load devices to the unstable state or cause damages to the load devices.